CXG1090EN high power 2 4 antenna switch mmic with integrated control logic description the CXG1090EN is a high power antenna switch mmic. this ic is suited to connect tx/rx to one of 4 antennas in cellular handset such as pdc. the CXG1090EN has the integrated control logic and can be operated with cmos input. this ic is designed using the sony's gaas j-fet process which enable the CXG1090EN to be operated with low voltage. features low insertion loss: 0.30db (typ.)@900mhz, 0.40db (typ.)@1.5ghz small package: 16-pin vson high power handling: pl db: 37dbm cmos compatible input control low bias voltage: v dd = 3.0v applications 2 4 antenna switch for digital cellular telephones such as pdc handsets structure gaas j-fet mmic absolute maximum ratings bias voltage v dd 7 v @ta = 25? control voltage v ctl 5 v @ta = 25? operating temperature topr ?5 to +85 ? storage temperature tstg ?5 to +150 ? note on handling gaas mmics are esd sensitive devices. special handling precautions are required. ?1 e00222b1y-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 16 pin vson (plastic)
?2 CXG1090EN block diagram rf5 (rx) rf4 (ant/ext.1) rf6 (diversity 1) rf2 (ant/ext. 2) rf3 (tx) rf1 (diversity 2) rf-gnd6 rf-gnd1 f1 f3 f6 f5 f7 f8 f2 f4 4 6 8 9 11 13 14 3 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rf4 gnd rf5 gnd rf6 rf-gnd6 v dd ctla rf3 gnd rf2 gnd rf1 rf-gnd1 ctlc ctlb recommended circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rf3 gnd gnd rf-gnd1 ctlc ctlb 100pf rf2 rf4 v dd ctla rf5 gnd gnd rf-gnd6 rf6 100pf 100pf 100pf l1 l1 l1 l1 100pf 100pf 100pf 100pf 1k ? 1k ? rf1 l1 l1 z6 z1 100pf 1k ? 100pf ? dc blocking capacitors (crf) are needed. ? recommended to use bypass capacitors (cbypass). ? recommended to use control resistors (rctl), when it is necessary to improve the electrostatic discharge strength (esd).
3 CXG1090EN truth table control on f1 f2 f3 f4 f5 f6 f7 f8 ctla h h l l l l l l l l h h l h l h l h rf3 rf2 rf3 rf4 rf5 rf2 rf5 rf4 rf5 rf6 rf5 rf1 off on on off off off on off off on off off off on on off off off on off off on off off off off off off on off off off off off off on on on on on off on on on on on on off ctlb ctlc dc bias condition (ta = 25 c) item v ctl (h) a to c v ctl (l) a to c v dd 2.4 0 2.8 3.6 0.8 3.2 v v v min. typ. max. unit
4 CXG1090EN electrical characteristics 1 (v ctl (l) = 0v, v ctl (h) = 3v, ta = 25 c) item frequency condition pin = 29.5dbm, v dd = 2.8 to 3.0v pin = 29.5dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 29.5dbm, v dd = 2.8 to 3.0v pin = 29.5dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 29.5dbm, v dd = 3.0v ? 1 pin = 29.5dbm, v dd = 2.8v ? 1 pin = 29.5dbm, v dd = 3.0v ? 1 pin = 29.5dbm, v dd = 2.8v ? 1 pin = 29.5dbm, v dd = 3.0v ? 1 pin = 29.5dbm, v dd = 2.8v ? 1 pin = 29.5dbm, v dd = 3.0v ? 1 pin = 29.5dbm, v dd = 2.8v ? 1 v dd = 3.0v v dd = 2.8v 17 17 17 17 31 24 0.32 0.30 0.55 0.55 0.5 0.5 19 21 21 19 38 29 67 67 75 75 67 67 67 67 85 0.45 0.4 1.0 0.55 0.55 0.85 0.85 0.8 0.8 1.4 57 55 65 62 60 57 60 57 150 1 0.9 5.0 db db db db db db db db db db db db dbc dbc dbc dbc dbc dbc dbc dbc a ma ma s rf3-rf2 rf3-rf4 rf5-rf2 rf5-rf4 rf5-rf1 rf5-rf6 rf3-rf2 rf3-rf4 rf5-rf2 rf5-rf4 rf5-rf1 rf5-rf6 each on port rf3-rf2 rf3-rf4 rf3-rf2 rf3-rf4 rf3-rf2 rf3-rf4 rf3-rf2 rf3-rf4 insertion loss isolation vswr acp (50khz) acp (100khz) 2nd harmonics 3nd harmonics control current bias current switching speed 889 to 960mhz 889 to 960mhz 810 to 885mhz 810 to 885mhz 810 to 885mhz 810 to 885mhz 889 to 960mhz 889 to 960mhz 810 to 885mhz 810 to 885mhz 810 to 885mhz 810 to 885mhz 810 to 960mhz 889 to 960mhz 889 to 960mhz 889 to 960mhz 889 to 960mhz min. typ. max. unit ? 1 input signal: acp (50khz) < 65dbc, acp (100khz) < 75dbc, 2nd harmonics < 65dbc, 3rd harmonics < 65dbc
5 CXG1090EN electrical characteristics 2 (v ctl (l) = 0v, v ctl (h) = 3v, ta = 25 c) item frequency condition pin = 29.5dbm, v dd = 2.8 to 3.0v pin = 29.5dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 29.5dbm, v dd = 2.8 to 3.0v pin = 29.5dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 7dbm, v dd = 2.8 to 3.0v pin = 29.5dbm, v dd = 3.0v ? 1 pin = 29.5dbm, v dd = 2.8v ? 1 pin = 29.5dbm, v dd = 3.0v ? 1 pin = 29.5dbm, v dd = 2.8v ? 1 pin = 29.5dbm, v dd = 3.0v ? 1 pin = 29.5dbm, v dd = 2.8v ? 1 pin = 29.5dbm, v dd = 3.0v ? 1 pin = 29.5dbm, v dd = 2.8v ? 1 v dd = 3.0v v dd = 2.8v 12 15 15 13 35 20 0.40 0.40 0.65 0.65 0.60 0.60 15 18 18 16 40 25 67 67 75 75 67 67 67 67 85 0.45 0.4 1.0 0.70 0.70 0.95 0.95 0.90 0.90 1.4 55 53 65 62 60 57 57 55 150 1 0.9 5.0 db db db db db db db db db db db db dbc dbc dbc dbc dbc dbc dbc dbc a ma ma s rf3-rf2 rf3-rf4 rf5-rf2 rf5-rf4 rf5-rf1 rf5-rf6 rf3-rf2 rf3-rf4 rf5-rf2 rf5-rf4 rf5-rf1 rf5-rf6 each on port rf3-rf2 rf3-rf4 rf3-rf2 rf3-rf4 rf3-rf2 rf3-rf4 rf3-rf2 rf3-rf4 insertion loss isolation vswr acp (50khz) acp (100khz) 2nd harmonics 3nd harmonics control current bias current switching speed 1429 to 1453mhz 1429 to 1453mhz 1477 to 1501mhz 1477 to 1501mhz 1477 to 1501mhz 1477 to 1501mhz 1429 to 1453mhz 1429 to 1453mhz 1477 to 1501mhz 1477 to 1501mhz 1477 to 1501mhz 1477 to 1501mhz 1429 to 1501mhz 1429 to 1453mhz 1429 to 1453mhz 1429 to 1453mhz 1429 to 1453mhz min. typ. max. unit ? 1 input signal: acp (50khz) < 65dbc, acp (100khz) < 75dbc, 2nd harmonics < 65dbc, 3rd harmonics < 65dbc
6 CXG1090EN package outline unit: mm 0.05 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating copper alloy package structure terminal section 0.2 0.01 0.23 0.02 0.03 0.03 soldrer plating 0.14 ranges of 0.1mm and 0.25mm from the end of a terminal. note: 1) the dimensions of the terminal section apply to the 16pin vson(plastic) vson-16p-01 0.02 g 0.2 s b a 3.5 2.7 2.5 0.4 b 0.2 s b a 0.05 m s a-b 2x 4x s s 0.9 max 0.6 0.5 0.2 0.13 0.025 + 0.09 0.03 1.4 0.35 0.1 0.35 0.1 sony corporation 0.05 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating copper alloy package structure terminal section 0.2 0.01 0.23 0.02 0.03 0.03 soldrer plating 0.14 ranges of 0.1mm and 0.25mm from the end of a terminal. note: 1) the dimensions of the terminal section apply to the 16pin vson(plastic) vson-16p-01 0.02 g 0.2 s b a 3.5 2.7 2.5 0.4 b 0.2 s b a 0.05 m s a-b 2x 4x s s 0.9 max 0.6 0.5 0.2 0.13 0.025 + 0.09 0.03 1.4 0.35 0.1 0.35 0.1 lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. kokubu ass'y
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